1. Field of the Invention
The present invention relates to communications and data transfer systems and more particularly to a method and apparatus for recovering data and an associated clock signal from a high speed data stream with high jitter tolerance. The invention further relates to a method for using a data activated sequential-logic phase detector and a digitally trimmed current controlled oscillator in a phase-locked loop to recover a clock from a data stream and sampling a data stream at three different phase positions of a recovered clock signal to produce a received data signal.
2. Related Technical Art
There is an increasing demand in the communications industry to provide high quality voice or analog services, and high speed, high volume, data communications. Especially in the areas of image transfer, on-line computer databases, accounting services, or central record systems, the demand for high volume digital data communications is rapidly increasing. In order to meet present demands and future communication needs, new digital networks are being proposed and developed which are capable of utilizing advanced digital switching, control, and communication technology to accommodate larger bandwidth signals and faster data transfer rates.
Digital networks propose to free communication system users from the restrictions of lower speed, 1200 to 9600 bits per second (bps), data transfers previously imposed by analog type communication circuits. New digital networks or network standards call for supporting data transfer speeds on the order of 64K or 64,000 bps with very low noise. As fiber optic links undergo further advancement and are placed into more extensive service, bandwidths and capacity for digital data transfer should increase by an order of magnitude to provide previously unrealized transfer rates on the order of 100M-600M bps.
Such significant increases in data transfer rates make real-time accounting, interactive communications and higher quality voice communications possible on a large national and international scale. Digital networks promise to eliminate the use of modems in many applications, provide low cost increases in data transfer capabilities, and allow different types of transmissions (voice, data, image, high or low speed) to be accommodated on a single transfer medium or link. Digital networks also provide relief from the error rate limitations imposed by older analog links which were inherently noisier and, therefore, more prone to create transmission errors.
While extension to a 64K bps standard technology represents a significant improvement, it is insufficient for accommodating all desired communication traffic being transferred into or through a network. That is, this higher transfer rate accommodates higher speeds and quality for single system users but is not capable of handling large numbers of similarly situated users. This has led to the development of multiplexed and encoded signals to provide multiples of the 64K bps signals. In the United States, data transfer circuits employing multiplexed 64K bps circuits are referred to as T-1 carriers and have total capacities of 1.56M bps or 24 channels of 64K bps capacity each. There are also higher capacity carriers, designated as T-3 carriers, which operate in the 44.736M bps data transfer range as an alternative for very large capacity data links. European standards currently include a 30 channel 2.049M bps link. In addition, to provide more cost efficient use of network capacity, individual communication signals for several smaller users (high speed or high quality) are often multiplexed, using Time Division Multiplexed (TDM) or Pulse Code Modulation (PCM) signal techniques, into a single channel on T-1 or T-3 carriers, or in digital networks.
However, as digital communications systems develop, such as the Integrated Service Digital Network (ISDN), they adopt stringent specifications and standards that must be accommodated by user interfacing equipment. That is, as the designs for advanced digital networks come into focus or closer to actual implementation, certain key operational requirements are imposed on system users. One such requirement is the amount of jitter tolerance allowed for interface equipment or devices. The key performance characteristic of any clock/data recovery circuit is its input jitter tolerance. The input jitter tolerance is the maximum amount of phase jittering on an input data stream tolerable by the circuit and still recover the clock and data. Current plans call for high jitter (tolerance rates at the 1.544 to 2.048M bps transfer speeds. These requirements challenge the current designs for Line Interface Units (LIU) which are the key communication elements needed for transfer of information between users and a network. Therefore, the network requirements also challenge the requirements for individual LIU components such as data detectors, filters, and phase-locked loops.
Carrier or network controllers track data transmissions and communicated digital information at the high network transfer rate or frequency until demultiplexed into individual communication signals. It is advantageous that networks are capable of accommodating a variety of communication signals having differing internal transfer rates and can allocate network bandwidth or resources, unequally, as required. However, a mechanism is required to track and lock onto the transfer rate of each individual communication signal when demultiplexed to assure proper decoding and information reception.
Each communication signal must have an internal or inherent clock associated with it for synchronizing digital data within the signal, and for proper data alignment and decoding. This internal or individual clock must be tracked and extracted or recovered at the time of reception by the LIU in order to detect and decode the data from the network or carrier. Therefore, the line interface unit must incorporate circuitry to recover both data and its associated clock from the network in order to function properly. However, synchronization with a local clock or oscillator often results in many problems. Clock and data recovery in the presence of noise and jitter, as well as at the required high transfer rates, has proven difficult. PG,6
Current approaches to tracking and recovering data fall into three general categories. These are: LC-tuned tank types, digital phase-locked loops, and analog phase-locked loops. LC tank-type circuits require the use of external components to determine or affect frequency tuning and are generally sensitive to patterns in the actual data being transferred. That is, patterns of high and low levels, and any harmonic components, occurring in the data as it is being received and passed through the LC circuits impact the LC tuning and make accurate data recovery difficult.
Digital phase-locked loop type circuits suffer high transfer rate phase problems such as effecting large frequency changes when encountering missing data pulses. Analog phase-locked loop type circuits provide fully integrated circuits with smooth clock outputs but require individual component optimization making products for generalized application difficult to achieve. Analog phase-locked loops also exhibit problems in accommodating significant quantities of input jitter.
One technique used to counter some of the problems encountered with jitter is use of an "elastic store". Data is received and temporarily stored while the clock is being recovered. The data is generally detected using a 90 degree phase shifted recovered clock in order to compensate for high frequency jitter which phase shifts the data. The recovered data can also be further retimed when transmitted or transferred from the store to remove the effects of low frequency line jitter. Typical circuits used to implement these functions accommodate jitter of +/-0.25 Unit Intervals (UI) or +/-90 degrees of phase error. However, this is not enough compensation for network requirements.
What is needed is a new method and apparatus for receiving a high speed data stream and recovering a clock and data embedded therein. The apparatus must be able to lock onto the frequency or clock rate of the data and continue to accurately track and recover the data in the presence of noise and jitter in the communication path or channel. It would also be beneficial to provide apparatus that is easily reduced to monolithic structures capable of mass production and low cost implementation.